SH7261 Datasheet, PDF (185/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.7 Interrupt Response Time
Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception handling starts and fetching of the first instruction in the
interrupt exception service routine begins. The interrupt processing operations differ in the cases
when banking is disabled, when banking is enabled without register bank overflow, and when
banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline
operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation
when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of
pipeline operation when banking is enabled with register bank overflow.
Table 6.5 Interrupt Response Time
Number of States
Item
Peripheral
NMI
User Break H-UDI
IRQ, PINT Module Remarks
Time from occurrence of
2 Icyc +
interrupt request until interrupt 2 Bcyc +
controller identifies priority,
1 Pcyc
compares it with mask bits in
SR, and sends interrupt request
signal to CPU
3 Icyc
2 Icyc +
1 Pcyc
2 Icyc +
3 Bcyc +
1 Pcyc
2 Icyc +
1 Bcyc +
1 Pcyc
Time from No
input of
register
interrupt
banking
request
signal to
CPU until
sequence
currently
being
executed is
completed,
interrupt
exception
handling
Register
banking
without
register
bank
overflow
starts, and Register
first
banking
instruction in with
interrupt
register
exception bank
service
overflow
routine is
fetched
Min. 3 Icyc + m1 + m2
Max. 4 Icyc + 2 (m1 + m2) + m3
Min. 
Max. 
Min. 
Max. 
3 Icyc + m1 + m2
12 Icyc + m1 + m2
3 Icyc + m1 + m2
3 Icyc + m1 + m2 + 19 (m4)
Min. is when the interrupt
wait time is zero.
Max. is when a higher-
priority interrupt request
has occurred during
interrupt exception
handling.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred
during execution of the
RESBANK instruction.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred
during execution of the
RESBANK instruction.
Rev. 2.00 Sep. 07, 2007 Page 153 of 1312
REJ09B0320-0200