SH7261 Datasheet, PDF (247/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.4.2 CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6)
CSnREC specifies the number of data recovery cycles to be inserted after read or write accesses.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————
WRCV[3:0]
————
RRCV[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R R R R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 28 
Initial
Value
All 0
27 to 24 WRCV[3:0] 0000
23 to 20 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Post-Write Data Recovery Cycle Setting
These bits specify the number of data recovery cycles
to be inserted after write accesses to the external bus.
If a value other than 0 is selected, between 1 and 15
data recovery cycles are inserted when a write access
to the external bus is followed by a read access to the
external bus. (Data recovery cycles are inserted even
when access is performed sequentially to the same
CSC channel.) Note that if idle cycles occur between
accesses to the external bus, the number of data
recovery cycles inserted is reduced by the number of
idle cycles.
0000: 0 cycle
0001: 1 cycles
:
1111: 15 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 215 of 1312
REJ09B0320-0200