SH7261 Datasheet, PDF (929/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB) [R5S72612] [R5S72613]
Initial
Bit
Bit Name Value R/W Description
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
RE
0
R/W Receive Enable
Enables/disables IEB reception. This bit must be set at
the initial setting before frame reception.
0: Reception is disabled.
1: Reception is enabled.
2 to 0 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20.3.2 IEBus Command Register (IECMR)
IECMR issues commands to control IEB communications. Since this register is a write-only
register, the read value is undefined.
IECMR is initialized by a power-on reset or in deep standby.
Bit: 7
6
5
4
3
2
1
0
—————
CMD
Initial value: 0
0
0
0
0
0
0
0
R/W: — — — — — W W W
Initial
Bit
Bit Name Value R/W Description
7 to 3 
All 0 
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 897 of 1312
REJ09B0320-0200