SH7261 Datasheet, PDF (368/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
8
ECLR
0
7 to 1 
All 0
R/W Description
R/W DMA Transfer Enable Clear
This bit specifies whether or not to clear the DMA
transfer enable bit (DEN) to "0" when the DMA transfer
end condition is detected.
When this bit is cleared to "0", the DMA transfer
enable bit (DEN) is not cleared to "0" even when the
DMA transfer end condition is detected.
When this bit is set to "1", the DMA transfer enable bit
(DEN) is cleared to "0" when the DMA transfer end
condition is detected.
Note: When a value is written to the DMA transfer
enable clear bit for a channel handling single
operand transfer, operation is not guaranteed.
0: Detection of the DMA transfer end condition does
not clear the DMA transfer enable bit to 0
1: Detection of the DMA transfer end condition clears
the DMA transfer enable bit to 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 336 of 1312
REJ09B0320-0200