SH7261 Datasheet, PDF (262/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value
R/W Description
7 to 4 DARFC
[3:0]
Undefined R/W
Initialization Auto-Refresh Count
These bits specify the number of times auto-refresh is
to be performed in the SDRAM initialization sequence.
0000: Setting prohibited
0001: 1 time
:
1111: 15 times
3 to 0 DARFI[3:0] Undefined R/W Initialization Auto-Refresh Interval
These bits specify the interval at which auto-refresh
commands are issued in the SDRAM initialization
sequence.
0000: 3 cycles
0001: 4 cycles
0010: 5 cycles
:
1111: 18 cycles
Note: Make settings that satisfy the specifications of the connected SDRAM before starting the
initialization sequence.
Rev. 2.00 Sep. 07, 2007 Page 230 of 1312
REJ09B0320-0200