SH7261 Datasheet, PDF (1195/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 Advanced User Debugger II (AUD-II)
29.3 RAM Monitor Mode
In this mode, all the modules connected to this LSI's internal or external bus can be read and
written to (except cache and H-UDI), allowing RAM monitoring and tuning to be carried out.
29.3.1 Communication Protocol
The AUD-II latches the AUDATA input when AUDSYNC is asserted. The following AUDATA
input format should be used.
0000
DIR
A3 to A0
A31 to A28 D3 to D0
Dn to Dn-3
Command
Address
Data (in case of write only)
B write: n = 7
W write: n = 15
L write: n = 31
Bit 3
Bit 2
Fixed at 1 0: Read
1: Write
Bit 1
Bit 0
00: Byte
01: Word
10: Longword
Spare bits (4 bits): B'0000
Figure 29.1 AUDATA Input Format
Rev. 2.00 Sep. 07, 2007 Page 1163 of 1312
REJ09B0320-0200