SH7261 Datasheet, PDF (1015/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.45 ISY Interrupt Source Mask Control Register (CROMST0M)
CROMST0M masks the ISY interrupt sources specified by the bits in the sync code status register
(CROMST0).
Bit: 7
—
Initial value: 0
R/W: R/W
6
—
0
R/W
5
4
3
2
1
0
ST_ ST_ ST_ ST_ ST_ ST_
SYILM SYNOM BLKSM BLKLM SECSM SECLM
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7, 6 
All 0 R/W Reserved
These bits are always read as 0.The write value should
always be 0.
5
ST_SYILM 0
R/W ISY interrupt ST_SYIL (bit 5 in the CROMST0 register)
source mask
4
ST_SYNOM 0
R/W ISY interrupt ST_SYNO (bit 4 in the CROMST0
register) source mask
3
ST_BLKSM 0
R/W ISY interrupt ST_BLKS (bit 3 in the CROMST0 register)
source mask
2
ST_BLKLM 0
R/W ISY interrupt ST_BLKL (bit 2 in the CROMST0 register)
source mask
1
ST_SECSM 0
R/W ISY interrupt ST_SECS (bit 1 in the CROMST0 register)
source mask
0
ST_SECLM 0
R/W ISY interrupt ST_SECL (bit 0 in the CROMST0 register)
source mask
Rev. 2.00 Sep. 07, 2007 Page 983 of 1312
REJ09B0320-0200