SH7261 Datasheet, PDF (104/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 3 Floating-Point Unit (FPU)
3.3.2 Floating-Point Status/Control Register (FPSCR)
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and
selects the rounding mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
         QIS  SZ PR DN
Cause
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
R/W: R R R R R R R R R R/W R R/W R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Cause
Enable
Flag
RM1 RM0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 23 —
Initial
Value
All 0
22
QIS
0
21
—
0
20
SZ
0
19
PR
0
18
DN
1
R/W _Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Nonnunerical Processing Mode
0: Processes qNaN or ±∞ as such
1: Treats qNaN or ±∞ as the same as sNaN (valid only
when the V bit in FPSCR enable is set to 1)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
pair (64 bits)
R/W Precision Mode
0: Floating-point instructions are executed as
single-precision operations
1: Floating-point instructions are executed as
double-precision operations (graphics support
instructions are undefined)
R
Denormalization Mode (Always fixed to 1 in SH2A-
FPU)
1: Denormalized number is treated as zero
Rev. 2.00 Sep. 07, 2007 Page 72 of 1312
REJ09B0320-0200