SH7261 Datasheet, PDF (569/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.5 Interrupt Sources
12.5.1 Interrupt Sources and Priorities
There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 6, Interrupt Controller (INTC).
Table 12.57 lists the MTU2 interrupt sources.
Table 12.57 MTU2 Interrupts
Channel Name
0
TGIA_0
TGIB_0
TGIC_0
TGID_0
TCIV_0
TGIE_0
TGIF_0
1
TGIA_1
TGIB_1
TCIV_1
TCIU_1
2
TGIA_2
TGIB_2
TCIV_2
TCIU_2
Interrupt Source
TGRA_0 input capture/compare match
TGRB_0 input capture/compare match
TGRC_0 input capture/compare match
TGRD_0 input capture/compare match
TCNT_0 overflow
TGRE_0 compare match
TGRF_0 compare match
TGRA_1 input capture/compare match
TGRB_1 input capture/compare match
TCNT_1 overflow
TCNT_1 underflow
TGRA_2 input capture/compare match
TGRB_2 input capture/compare match
TCNT_2 overflow
TCNT_2 underflow
DMAC
Interrupt Flag Activation
TGFA_0
Possible
TGFB_0
Not possible
TGFC_0
Not possible
TGFD_0
Not possible
TCFV_0
Not possible
TGFE_0
Not possible
TGFF_0
Not possible
TGFA_1
Possible
TGFB_1
Not possible
TCFV_1
Not possible
TCFU_1
Not possible
TGFA_2
Possible
TGFB_2
Not possible
TCFV_2
Not possible
TCFU_2
Not possible
Priority
High
Low
Rev. 2.00 Sep. 07, 2007 Page 537 of 1312
REJ09B0320-0200