SH7261 Datasheet, PDF (591/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel
5, write to TGR is performed and the input capture signal is generated.
Figures 12.116 and 12.117 show the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T1 T2
TGR address
M
TGR
M
Figure 12.116 Contention between TGR Write and Input Capture (Channels 0 to 4)
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1 T2
TGR address
M
TGR write data
N
Figure 12.117 Contention between TGR Write and Input Capture (Channel 5)
Rev. 2.00 Sep. 07, 2007 Page 559 of 1312
REJ09B0320-0200