SH7261 Datasheet, PDF (392/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Direct Memory Access Controller (DMAC)
11.7.3 Sense Mode for DMA Requests
When pins DREQ0 to DREQ3 (DCTG = "000001" to "000100") are specified by the DMA
request source selection bits (DTCG), either level sense or edge sense might be required. Make the
appropriate setting ("01" or "11" for level sense and "00" or "10" for edge sense) in the input sense
selection bits (STRG) of DMA control register A (DMCNTAn).
When the software trigger (DCTG = "000000") is selected as a DMA request source, set these bits
to "00" to select the rising-edge sense. When IIC3, SCIF, SSI, RCAN-ET, MTU2, or ADC
(DCTG = "000101" to "100101") is selected, set the bits to "10" to select the falling-edge sense.
Table 11.4 shows the relationships between the DMA request sources and input sense mode.
Below are further details on level- and edge-sense operation.
(1) Level Sense
When a level sense is specified (STRG = "01" or "11"), one level of the DMA request signal
indicates the DMA request. Since DMA requests detected in this way are not retained in the
DMAC, maintain the requesting level until acceptance of the DMA request has been confirmed.
Figure 11.7 is an example of DMA request reception processing when a level sense has been
selected.
System clock
DMA state
DMA request input
(low level sense)
Start of single operand transfer
Read
Maintain DMA request level until DMA acknowledge output
is activated to indicate acceptance of the request
Write
DMA acknowledge
output
DMA request bit
[Legend]
: Sampling point for DMA request
Figure 11.7 Example of DMA Request Reception Processing for a Level Sense
When a level sense has been selected, DMA request bit for the channel is masked over the period
from the start of the last write access of single operand transfer until four clock pulses (system
Rev. 2.00 Sep. 07, 2007 Page 360 of 1312
REJ09B0320-0200