SH7261 Datasheet, PDF (648/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 8-Bit Timers (TMR)
13.5.2 Timing of CMFA and CMFB Setting at Compare Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT
values match, the compare match signal is not generated until the next TCNT clock input. Figure
13.6 shows this timing.
Pφ
TCNT
N
TCOR
N
Compare match
signal
CMF
N+1
Figure 13.6 Timing of CMF Setting at Compare Match
13.5.3 Timing of Timer Output at Compare Match
When a compare match signal is generated, the timer output changes as specified by bits OS3 to
OS0 in TCSR. Figure 13.7 shows the timing when the timer output is toggled by the compare
match A signal.
Pφ
Compare match A
signal
Timer output pin
Figure 13.7 Timing of Toggled Timer Output at Compare Match A
Rev. 2.00 Sep. 07, 2007 Page 616 of 1312
REJ09B0320-0200