SH7261 Datasheet, PDF (279/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
4. Tdw1 to Tdwn (Write Data Output Delay Cycle)
In write access write data output delay cycles are inserted between the wait end cycle and the
following page access if the write data output delay wait setting is other than 0. Assertion of
the address and output data is extended for the duration of this interval. Also, the WR signal is
negated (high level).
5. Tpw1 to Tpwn (Page Read Cycle Wait, Page Write Cycle Wait)
In page access the page read cycle wait and page write cycle wait settings are used in place of
the read cycle wait and write cycle wait settings for the second and subsequent bus cycles. The
WR assert wait setting works the same as during the first bus cycle. The RD assert wait setting
operates differently depending on the page read access mode (PRMOD) setting value.
PRMOD = 0: RD assert wait setting operates identically to first bus cycle.
PRMOD = 1: RD assert wait setting is invalid. Operation is the same as an RD assert wait
setting of 0.
6. Tend/Tdw1 to Tdwn (Wait End Cycle/Write Data Output Delay Cycle)
These operate the same as during the first access (3 and 4 above).
7. Tn1 to Tnm (CS Delay Cycle)
These are the cycles between the final wait end cycle and when CSn is negated (high level).
The number of CS delay cycles is counted beginning from the wait end cycle.
8. Trd (Final Read Data Sample Cycle)
This is the final sample cycle for read data.
(3) External Wait Function
The external wait signal (WAIT) can be used to extend the wait cycle duration beyond the value
specified by the cycle wait (CSRWAIT, CSWWAIT) or page access cycle wait (CSPRWAIT,
CSPWWAIT) settings in the CSn wait control register (CSWCNTn). If external wait enable
(EWENB = 1) has been selected, wait cycles are inserted for as long as the WAIT signal remains
low level. The WAIT signal is disabled if external wait disable (EWENB = 0) has been selected.
Note that the wait cycles specified by the settings of the CSn wait control register (CSWCNTn)
are inserted regardless of the state of the WAIT signal.
(a) Normal Read/Write Operation
The WAIT signal is sampled all the time and its result is reflected two cycles later. Thus, when the
WAIT signal is low two cycles before the end of the wait cycles, external cycles are inserted.
After the WAIT signal has gone high, the wait cycles end two cycles later.
Rev. 2.00 Sep. 07, 2007 Page 247 of 1312
REJ09B0320-0200