SH7261 Datasheet, PDF (208/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
Bit
6
5
4 to 0
Bit Name
PCB1
Initial
Value
0
PCB0
0

All 0
R/W Description
R/W PC Break Select 1
Selects the break timing of the instruction fetch cycle
for channel 1 as before or after instruction execution.
0: PC break of channel 1 is generated before
instruction execution
1: PC break of channel 1 is generated after instruction
execution
R/W PC Break Select 0
Selects the break timing of the instruction fetch cycle
for channel 0 as before or after instruction execution.
0: PC break of channel 0 is generated before
instruction execution
1: PC break of channel 0 is generated after instruction
execution
R Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 176 of 1312
REJ09B0320-0200