SH7261 Datasheet, PDF (327/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Bus Monitor
Table 10.2 Bus Space and Slave Bus
Address
Bus Space
Slave Bus
H'0000 0000 to H'4FFF FFFF External bus space
H'5000 0000 to H'E7FF FFFF Reserved
External bus
(Others*¹)
H'E800 0000 to H'E800 FFFF
H'E801 0000 to H'EFFF FFFF
H'F000 0000 to H'F1FF FFFF
H'F200 0000 to H'F5FF FFFF
H'F600 0000 to H'FF3F FFFF
On-chip peripheral module (3)
Reserved
Address array space in cache
Reserved
Reserved
Peripheral bus (3)
(Others*¹)
*²
*²
(Others*¹)
H'FF40 0000 to H'FF5F FFFF
H'FF60 0000 to H'FFF7 FFFF
H'FFF8 0000 to H'FFF8 7FFF
H'FFF8 8000 to H'FFFB FFFF
On-chip peripheral module (1)
Reserved
On-chip RAM
Reserved
Peripheral bus (1)
(Others*¹)
*²
*²
H'FFFC 0000 to H'FFFF FFFF On-chip peripheral module (2) Peripheral bus (2)
Notes: 1. This means bus spaces in the slave bus space other than those for the external bus
and peripheral buses (1), (2), and (3).
2. An illegal address access error does not occur.
10.1.3 Bus Monitor Status Register 2 (SYCBESTS2)
SYCBESTS2 indicates the status of slave buses (external bus/peripheral bus (2)/others) regarding
whether a timeout occurred, whether an illegal address access was made, or which bus master
accessed the slave bus.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— ETO EER — — — EMST[1:0] — — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — OER — — — OMST[1:0] — — SHER — — — SHMST[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Rev. 2.00 Sep. 07, 2007 Page 295 of 1312
REJ09B0320-0200