SH7261 Datasheet, PDF (1309/1348 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 31 Electrical Characteristics
31.3.6 MTU2 Module Timing
Table 31.10 MTU2 Module Timing
Conditions: PV_CC = V_CCR = PLLV_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V,
PV_CC − 0.3 V ≤ AV_CC ≤ PV_CC, AV_ref = 3.0 V to AV_CC,
PV_SS = V_SSR = PLLV_SS = AV_SS = 0 V
Item
Symbol Min.
Max. Unit Figure
Output compare output delay time t_TOCD

100 ns Figure 31.25
Input capture input setup time
t
TICS
(n
−
1)
×
t /2
cyc
+
20

ns
Timer input setup time
t
TCKS
(n
−
1)
×
t
cyc
+
20

ns Figure 31.26
Timer clock pulse width (single edge) t
1.5
TCKWH/L

t
pcyc
Timer clock pulse width (both edges) t
2.5
TCKWH/L

t
pcyc
Timer clock pulse width
(phase counting mode)
t_TCKWH/L
2.5

t_pcyc
Note: Above is the case in which the clock ratio B:P = n:1 (n = 1, 2, 3, 4, 6, 8, or 12)
t
pcyc
indicates
peripheral
clock
(Pφ)
cycle.
CKIO
Output compare
output
Input capture
input
t_TOCD
t_TICS
Figure 31.25 MTU2 Input/Output Timing
CKIO
TCLKA to
TCLKD
t_TCKS
t_TCKS
t_TCKWL
t_TCKWH
Figure 31.26 MTU2 Clock Input Timing
Rev. 2.00 Sep. 07, 2007 Page 1277 of 1312
REJ09B0320-0200