82NM10 Datasheet, PDF (98/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.5.1.2
Start Field Definition
Table 5-34.Start Field Bit Definitions
Bits[3:0]
Encoding
Definition
0000
0010
0011
1111
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a
target.
NOTE: All other encodings are Reserved.
5.5.1.3
Cycle Type / Direction (CYCTYPE + DIR)
Chipset drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0. Table 5-35 shows the valid bit encodings.
Table 5-35.Cycle Type Bit Definitions
Bits[3:2] Bit1
Definition
00
0
I/O Read
00
1
I/O Write
10
0
DMA Read
10
1
DMA Write
11
x
Reserved. If a peripheral performing a bus master cycle generates this
value, Chipset aborts the cycle.
NOTE: All other encodings are Reserved.
5.5.1.4
SIZE
Bits[3:2] are reserved. Chipset drives them to 00. Peripherals running bus master
cycles are also supposed to drive 00 for bits 3:2; however, Chipset ignores those bits.
Bits[1:0] are encoded as listed in Table 5-36.
Table 5-36.Transfer Size Bit Definition
Bits[1:0]
Size
00
8-bit transfer (1 byte)
01
16-bit transfer (2 bytes)
10
Reserved. Chipset does not drive this combination. If a peripheral running a bus
master cycle drives this combination, Chipset may abort the transfer.
11
32-bit transfer (4 bytes)
98
Datasheet