82NM10 Datasheet, PDF (574/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Table 18-146.Intel HD Audio PCI Register Address Map
(Intel HD Audio D27:F0) (Sheet 3 of 3)
Offset Mnemonic
Register Name
140h–143h
148h–14Bh
L1DESC
L1ADDL
Link 1 Description
Link 1 Lower Address
14Ch–14Fh L1ADDU Link 1 Upper Address
Default
00000001h
See Register
Description
00000000h
Access
RO
RO
RO
18.1.1
VID—Vendor Identification Register
(Intel HD Audio Controller—D27:F0)
Offset:
00h-01h
Attribute:
RO
Default Value:
8086hSize:16 bits
Bit
Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
18.1.2
DID—Device Identification Register
(Intel HD Audio Controller—D27:F0)
Offset Address: 02h–03h
Default Value: See bit description
Attribute:
Size:
Bit
15:0
Device ID — RO. T
Description
RO
16 bits
18.1.3
PCICMD—PCI Command Register
(Intel HD Audio Controller—D27:F0)
Offset Address: 04h–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11
10
Reserved
Interrupt Disable (ID) — R/W.
0= The INTx# signals may be asserted.
1= The Intel HD Audio controller’s INTx# signal will be de-asserted
NOTE: This bit does not affect the generation of MSIs.
9
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
8
SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the Chipset Intel
High Definition Audio Controller.
7
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
6
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
5
VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
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