82NM10 Datasheet, PDF (66/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Pin States
The chipset core well signal states are indeterminate and undefined and may glitch,
including input signals acting as outputs, prior to PWROK assertion. This does not apply
to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK
assertion.
Table 3-26.Power Plane and States for Output and I/O Signals (Sheet 1 of 4)
Signal Name
Power
Plane
During
PLTRST#⁶ /
RSMRST#⁷
Immediately
after
PLTRST#⁶ /
RSMRST#⁷
C3/C4
S1
S3_COLD13
S4/
S5
PETp[4:1],
PETn[4:1]
Core
PCI Express*
High
High¹²
Defined Defined
Off
Off
DMI[3:0]TXP,
DMI[3:0]TXN
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
GNT[2:1]#
STRAP1#/GPIO48
STRAP2#/GPIO17
IRDY#, TRDY#
PAR
PCIRST#
PERR#
PLOCK#
STOP#
LAD[3:0] /
FWH[3:0]
LFRAME#
EE_CS
EE_DOUT
EE_SHCLK
LAN_RSTSYNC
LAN_TXD[2:0]
Core
High
DMI
High¹²
Defined Defined
Core
Core
Core
Core
Core
Core
Core
Suspend
Core
Core
Core
Core
PCI Bus
Low
Low
High-Z
High-Z
High with
Internal Pull-
ups
Undefined
Undefined
High-Z
High-Z
High
High-Z
Low
Low
High-Z
High-Z
High-Z
High-Z
Undefined
High
High-Z
High-Z
High-Z
High
LPC Interface
High
Defined
Defined
High-Z
High-Z
High
Defined
Defined
High-Z
High-Z
High
High-Z
Defined
High
High-Z
High-Z
High-Z
High-Z
Defined
High
High-Z
High-Z
High-Z
High
High
Core
LAN
LAN
LAN
LAN
LAN
High
High
High
LAN Connect and EEPROM Interface
Low
Running
Defined
High
High-Z
High
Low
High
Running
Low
Low
Defined
Defined
Defined
Defined
High
Defined
Defined
Defined
Defined
Defined
Off
Off
Off
Off
Off
Off
Off
Off
Low
Off
Off
Off
Off
Off
Note 4
Note 4
Note 4
Note 4
Note 4
Off
Off
Off
Off
Off
Off
Off
Off
Low
Off
Off
Off
Off
Off
Note 4
Note 4
Note 4
Note 4
Note 4
66
Datasheet