82NM10 Datasheet, PDF (482/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
15:14
13:12
Reserved
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of
these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these bits.
SCB1 = 0
(33 MHz clk)
00 = CT 4 clocks, RP 6
clocks
01 = CT 3 clocks, RP 5
clocks
10 = CT 2 clocks, RP 4
clocks
11 = Reserved
SCB1 = 1
(66 MHz clk)
FAST_SCB1 = 1
(133 MHz clk)
00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 8 01 = CT 3 clocks, RP
clocks
16 clocks
10 = CT 2 clocks, RP 8
clocks
10 = Reserved
11 = Reserved
11 = Reserved
11:10 Reserved
9:8 Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of
these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these bits.
SCB1 = 0
(33 MHz clk)
00 = CT 4
clocks, RP 6
clocks
01 = CT 3
clocks, RP 5
clocks
10 = CT 2
clocks, RP 4
clocks
11 = Reserved
SCB1 = 1
(66 MHz clk)
00 = Reserved
FAST_SCB1 = 1
(133 MHz clk)
00 = Reserved
01 = CT 3 clocks, 01 = CT 3 clocks, RP
RP 8 clocks
16 clocks
10 = CT 2 clocks, 10 = Reserved
RP 8 clocks
11 = Reserved 11 = Reserved
7:6 Reserved
5:4 Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these
bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP
(RP) time is also determined by the setting of these bits.
PCB1 = 0
(33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1
(66 MHz clk)
00 = Reserved
01 = CT 3 clocks,
RP 8 clocks
10 = CT 2 clocks,
RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 (133 MHz
clk)
00 = Reserved
01 = CT 3 clocks, RP 16
clocks
10 = Reserved
11 = Reserved
3:2 Reserved
482
Datasheet