82NM10 Datasheet, PDF (203/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-77.Enable for SMBALERT#
Event
INTREN
(Host Control
I/O Register,
Offset 02h,
Bit 0)
SMBALERT#
X
asserted low
(always
X
reported in
Host Status
Register, Bit
1
5)
SMB_SMI_EN
(Host
Configuration
Register,
D31:F3:Offset
40h, Bit 1)
X
1
0
SMBALERT_DIS
(Slave Command
I/O Register,
Offset 11h, Bit 2)
Result
X
Wake generated
0
Slave SMI#
generated
(SMBUS_SMI_STS)
0
Interrupt generated
Table 5-78.Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration
Register,
D31:F3:Offset 40h,
Bit1)
Event
Slave Write to
X
Wake/SMI#
Command
Slave Write to
X
SMLINK_SLAVE_S
MI Command
Any combination of
0
Host Status
Register [4:1]
1
asserted
1
X
Wake generated when
asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
X
Slave SMI# generated when
in the S0 state
(SMBUS_SMI_STS)
X
None
0
Interrupt generated
1
Host SMI# generated
Table 5-79.Enables for the Host Notify Command
HOST_NOTIFY_INTRE
N (Slave Control I/O
Register, Offset 11h,
bit 0)
SMB_SMI_EN
(Host Config
Register,
D31:F3:Off40h, Bit
1)
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h,
bit 1)
Result
0
X
0
None
X
X
1
Wake generated
1
0
X
Interrupt generated
1
1
X
Slave SMI#
generated
(SMBUS_SMI_STS)
Datasheet
203