82NM10 Datasheet, PDF (171/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
Note:
Chipset supports all of the mandatory features of the Serial ATA Advanced Host
Controller Interface Specification, Revision 1.0 and many optional features, such as
hardware assisted native command queuing, aggressive power management, LED
indicator support, and Hot-Plug thru the use of interlock switch support (additional
platform hardware and software may be required depending upon the implementation).
For reliable device removal notification while in AHCI operation without the use of
interlock switches (surprise removal), interface power management should be disabled
for the associated port. See Section 7.3.1 of the AHCI Specification for more
information.
When there are more than two PRD entries for a PIO data transfer that spans multiple
DATA FISes, Chipset does not support intermediate PRD entries that are less than 144
Words in size when Chipset is operating in AHCI mode at 1.5 Gb/s.
5.17
High Precision Event Timers
This function provides a set of timers that can be used by the operating system. The
timers are defined such that in the future, the operating system may be able to assign
specific timers to used directly by specific applications. Each timer can be configured to
cause a separate interrupt.
Chipset provides three timers. The three timers are implemented as a single counter
each with its own comparator and value register. This counter increases monotonically.
Each individual timer can generate an interrupt when the value in its value register
matches the value in the main counter.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; however, the BIOS sets this space prior to
handing it over to the operating system
(See Section 9.4). It is not expected that the operating system will move the location
of these timers once it is set by the BIOS.
5.17.1
Timer Accuracy
1. The timers are accurate over any 1 ms period to within 0.05% of the time specified
in the timer resolution fields.
2. Within any 100 microsecond period, the timer reports a time that is up to two ticks
too early or too late. Each tick is less than or equal to 100 ns, so this represents an
error of less than 0.2%.
3. The timer is monotonic. It does not return the same value on two consecutive
reads (unless the counter has rolled over and reached the same value).
Datasheet
171