82NM10 Datasheet, PDF (567/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
Bit
Description
0 CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the
DERR bit of the host status register will also be set. This bit will be set by the
controller if a software abort occurs in the middle of the CRC portion of the cycle or
an abort happens after the Chipset has received the final data bit transmitted by an
external slave.
17.2.12 AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Dh
Attribute:
R/W
Default Value: 00h
Size:
8 bits
Lockable:
No
Power Well:
Resume
.
Bit
Description
7:2 Reserved
1 Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable.
1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as
opposed to a single register. This enables the block commands to transfer or receive
up to 32-bytes before the Chipset generates an interrupt.
0 Automatically Append CRC (AAC) — R/W.
0 = Chipset will Not automatically append the CRC.
1 = The Chipset will automatically append the CRC. This bit must not be changed during
SMBus transactions or undetermined behavior will result. It should be programmed
only once during the lifetime of the function.
17.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 0Eh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
This register is only applicable in the TCO compatible mode.
Datasheet
567