82NM10 Datasheet, PDF (53/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
Table 2-13.Power Management Interface Signals (Sheet 2 of 3)
Name
SYS_RESET#
RSMRST#
LAN_RST#
WAKE#
MCH_SYNC#
SUS_STAT# /
LPCPD#
SUSCLK
VRMPWRGD
BM_BUSY#/
GPIO0
CLKRUN#
STP_PCI#
STP_CPU#
Type
Description
System Reset: This pin forces an internal reset after being
I
debounced. The chipset will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle
before forcing a reset on the system.
I
Resume Well Reset: This signal is used for resetting the resume
power plane logic.
LAN Reset: When asserted, the internal LAN controller will be put
into reset. This signal must be asserted for at least 10 ms after the
I resume well power is valid. When deasserted, this signal is an
indication that the resume well power is stable.
NOTE: LAN_RST# should be tied to RSMRST#.
I
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.
MCH SYNC: This input is internally ANDed with the PWROK input.
I _{Connect to the ICH_SYNC# output of (G)MCH. This signal need to}
pull-up to VCC3_3 when the chipset is not pair with (G)MCH.
Suspend Status: This signal is asserted by The chipset to indicate
that the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
O refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC interface.
O
Suspend Clock: This clock is an output of the RTC generator circuit
to use by other chips for refresh clock.
VRM Power Good: This should be connected to be the processor’s
I VRM Power Good signifying the VRM is stable. This signal is internally
ANDed with the PWROK input.
Bus Master Busy: This signal supports the C3 state. It provides an
indication that a bus master device is busy. When this signal is
asserted, the BM_STS bit will be set. If this signal goes active in a C3
I state, it is treated as a break event.
NOTE: This signal is internally synchronized using the PCICLK and a
two-stage synchronizer. It does not need to meet any
particular setup or hold time.
PCI Clock Run: This clock supports the PCI CLKRUN protocol. It
I/O connects to peripherals that need to request clock restart or
prevention of clock stopping.
Stop PCI Clock: This signal is an output to the external clock
O
generator for it to turn off the PCI clock. It is used to support PCI
CLKRUN# protocol. If this functionality is not needed, this signal can
be configured as a GPIO.
Stop CPU Clock: This signal is an output to the external clock
O
generator for it to turn off the processor clock. It is used to support
the C3 state. If this functionality is not needed, this signal can be
configured as a GPIO.
Datasheet
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