82NM10 Datasheet, PDF (570/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
Bit
Description
0 HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation
of interrupt or SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This
enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is
generated, either PIRQB# or SMI# is generated, depending on the value of the
SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this bit
is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or
SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
17.2.17 NOTIFY_DADDR—Notify Device Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 14h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:1 DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during
the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider
this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to
1.
0 Reserved
17.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 16h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:0 DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)
is set to 1.
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Datasheet