82NM10 Datasheet, PDF (183/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.19.1.1
BIOS Initialization
BIOS performs a number of platform customization steps after the core well has
powered up. Contact your Intel Field Representative for additional Chipset BIOS
information.
5.19.1.2
Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0.
5.19.1.3
EHC Resets
In addition to the standard Chipset hardware resets, portions of the EHC are reset by
the HCRESET bit and the transition from the D3_HOT device power management state to
the D0 state. The effects of each of these resets are:
Reset
Does Reset
Does not Reset
Comments
HCRESET bit set.
Software writes
the Device Power
State from D3_HOT
(11b) to D0
(00b).
Memory space
registers except
Structural
Parameters (which is
written by BIOS).
Core well registers
(except BIOS-
programmed
registers).
Configuration
registers.
Suspend well
registers; BIOS-
programmed core
well registers.
The HCRESET must only affect
registers that the EHCI driver
controls. PCI Configuration
space and BIOS-programmed
parameters can not be reset.
The D3-to-D0 transition must
not cause wake information
(suspend well) to be lost. It also
must not clear BIOS-
programmed registers because
BIOS may not be invoked
following the D3-to-D0
transition.
If the detailed register descriptions give exceptions to these rules, those exceptions
override these rules. This summary is provided to help explain the reasons for the reset
policies.
5.19.2
Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 for details.
5.19.3
USB 2.0 Enhanced Host Controller DMA
Chipset USB 2.0 EHC implements three sources of USB packets. They are, in order of
priority on USB during each microframe:
1. The USB 2.0 Debug Port (see Section 5.19.10),
2. The Periodic DMA engine, and
3. The Asynchronous DMA engine. Chipset always performs any currently-pending
debug port transaction at the beginning of a microframe, followed by any pending
Datasheet
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