82NM10 Datasheet, PDF (401/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.6.2.4
Bit
Description
5 Alarm Flag (AF) — RO.
0 = This bit is cleared upon RTCRST# or a read of Register C.
1 = Alarm Flag will be set after all Alarm values match the current time.
4 Update-Ended Flag (UF) — RO.
0 = The bit is cleared upon RSMRST# or a read of Register C.
1 = Set immediately following an update cycle for each second.
3:0 Reserved. Will always report 0.
RTC_REGD—Register D (Flag Register)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Dh
Attribute:
10UUUUUU (U: Undefined) Size:
No
Power Well:
R/W
8-bit
RTC
Bit
Description
7 Valid RAM and Time Bit (VRT) — R/W.
0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for
read cycles.
1 = This bit is hardwired to 1 in the RTC power well.
6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.
5:0 Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b,
then a don’t care state is assumed. The host must configure the date alarm for these
bits to do anything, yet they can be written at any time. If the date alarm is not
enabled, these bits will return 0’s to mimic the functionality of the Motorola 146818B.
These bits are not affected by any reset assertion.
13.7
Processor Interface Registers (LPC I/F—D31:F0)
Table 13-126 is the register address map for the processor interface registers.
Table 13-126.Processor Interface PCI Register Address Map (LPC I/F—D31:F0)
Offset Mnemonic
Register Name
Default
Type
61h
70h
92h
F0h
CF9h
NMI_SC
NMI_EN
PORT92
COPROC_ERR
RST_CNT
NMI Status and Control
NMI Enable
Fast A20 and Init
Coprocessor Error
Reset Control
00h
R/W, RO
80h
R/W (special)
00h
R/W
00h
R/W
00h
R/W
Datasheet
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