82NM10 Datasheet, PDF (238/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Electrical Characteristics
Table 8-105.Power Management Timings (Sheet 1 of 3)
Sym
Parameter
t230 VccSus active to SLP_S5#, SLP_S4#,
SLP_S3#, SUS_STAT#, PLTRST# and
PCIRST#active
t231 RSMRST# inactive to SUSCLK running,
t232 ^{SLP_S5# inactive}
t233 SLP_S5# inactive to SLP_S4# inactive
Min Max Units Notes
50
ns
110
ms
1, 2
See Note Below
3
t234 SLP_S4# inactive to SLP_S3# inactive
1
2 RTCCLK
4
t250 Processor I/F signals latched prior to
STPCLK# active
(Netbook Only)
t253 DPSLP# active to STP_CPU# active
(Netbook Only)
t254 STP_CPU# active to processor clock stopped
(Netbook Only)
t255 STP_CPU# active to DPRSTP#, DPRSLPVR
active
(Netbook Only)
t265
Break Event to DPRSTP#, DPRSLPVR
inactive
(C4 Exit)
(Netbook Only)
t266 DPRSLPVR, DPRSTP# inactive to STP_CPU#
inactive and CPU Vcc ramped
(Netbook Only)
t267
Break Event to STP_CPU# inactive
(C3 Exit)
(Netbook Only)
t268 STP_CPU# inactive to processor clock
running
(Netbook Only)
t269 STP_CPU# inactive to DPSLP# inactive
(Netbook Only)
t271 S1 Wake Event to CPUSLP# inactive
(Nettop Only)
t273
Break Event to STPCLK# inactive
(C2 Exit)
(Netbook Only)
t274 STPCLK# inactive to processor I/F signals
unlatched
(Netbook Only)
0
1
1
0
–
0
1.5 1.8
Programable.
See
D31:F0:AA,
bits 3:2
6
Note
14
0
3
1
1
1
25
0
8
9
PCICLK
PCICLK
µs
µs
PCICLK
PCICLK
PCICLK
PCICLK
ns
PCICLK
5
6
6, 7
8
6, 9, 10
6, 7
6, 11
6
5, 6
Fig
8-34
8-35
8-34
8-35
8-34
8-35
8-34
8-35
8-41
8-43
8-42
8-43
8-43
8-43
8-43
8-43
8-42
8-43
8-42
8-43
8-36
8-41
8-41
8-43
238
Datasheet