82NM10 Datasheet, PDF (638/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.31 SLCTL—Slot Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 58h–59h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:13 Reserved
12 Link Active Changed Enable (LACE) — RW.
0 = Disable.
1 = Enables generation of a hot plug interrupt when the Data Link Layer Link Active
field (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed.
11 Reserved
10 Power Controller Control (PCC) — RO.This bit has no meaning for module based
Hot-Plug.
9:8 Power Indicator Control (PIC) — R/W. When read, the current state of the power
indicator is returned. When written, the appropriate POWER_INDICATOR_* messages
are sent. Defined encodings are:
Bits
00b
01b
10b
11b
Definition
Reserved
On
Blink
Off
7:6 Attention Indicator Control (AIC) — R/W. When read, the current state of the
attention indicator is returned. When written, the appropriate
ATTENTION_INDICATOR_* messages are sent. Defined encodings are:
Bits
00b
01b
10b
11b
Definition
Reserved
On
Blink
Off
5 Hot Plug Interrupt Enable (HPE) — R/W.
0 = Disable. Hot plug interrupts based on Hot-Plug events is disabled.
1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events.
4 Command Completed Interrupt Enable (CCE) — R/W.
0 = Disable. Hot plug interrupts based on command completions is disabled.
1 = Enables the generation of a Hot-Plug interrupt when a command is completed by
the Hot-Plug controller.
3 Presence Detect Changed Enable (PDE) — R/W.
0 = Disable. Hot plug interrupts based on presence detect logic changes is disabled.
1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence
detect logic changes state.
2 MRL Sensor Changed Enable (MSE) — R/W. MSE not supported.
1 Power Fault Detected Enable (PFE) — R/W. PFE not supported.
638
Datasheet