82NM10 Datasheet, PDF (329/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
Bit
Description
5 PET VLAN Enable (ENA_VLAN) — R/W.
0 = Disable
1 = Indicates a VLAN header for PET
NOTE: If this bit is set, the PET packet in EEPROM must have the VLAN tag within the
packet.
4 Reserved
3 System Power Cycle Enable (ENA_CYCLE) — R/W.
0 = Disable
1 = Enables RMCP Power Cycle action.
2 System Power-Down Enable (ENA_DWN) — R/W.
0 = Disable
1 = Enables RMCP Power-Down action.
1 System Power-Up Enable (ENA_UP) — R/W.
0 = Disable
1 = Enables RMCP Power-Up action.
0 System Reset Enable (ENA_RST) — R/W.
0 = Disable
1 = Enables RMCP Reset action
11.3.6
APM—APM Register
(ASF Controller—B1:D8:F0)
Offset Address: E5h
Default Value: 08h
Attribute:
Size:
R/W
8 bits
This register contains the configuration bit to disable state-based security.
Bit
Description
7:4 Reserved
3 Disable State-based Security (APM_DISSB) — R/W.
0 = State-based security on OSHung is enabled.
1 = State-based security is disabled and actions are not gated by OSHung.
2:0 Reserved
11.3.7
WTIM_CONF—Watchdog Timer Configuration Register
(ASF Controller—B1:D8:F0)
Offset Address: E8h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register contains a single bit that enables the Watchdog timer. This bit is not
intended to be accessed by software, but should be configured appropriately in the
EEPROM location for this register default. The bit provides real-time control for
enabling/disabling the Watchdog timer. When set the timer will count down. When
cleared the counter will stop. Timer Start ASF SMBUS messages will set this bit. Timer
Stop ASF SMBus transactions will clear this bit.
Datasheet
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