82NM10 Datasheet, PDF (346/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
13
12
11
10:9
8
7
6
5
4:0
Received Master Abort (RMA) — R/WC.
0 = No master abort.
1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the
cycle is master-aborted. For (G)MCH or CPU/Chipset interface packets that have
completion required, this must also cause a target abort to be returned and sets
PSTS.STA. (D30:F0:06 bit 11)
Received Target Abort (RTA) — R/WC.
0 = No target abort.
1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is
target-aborted on PCI. For (G)MCH or CPU/Chipset interface packets that have
completion required, this event must also cause a target abort to be returned, and
sets PSTS.STA. (D30:F0:06 bit 11).
Signaled Target Abort (STA) — R/WC.
0 = No target abort.
1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a
target abort.
DEVSEL# Timing (DEVT) — RO.
01h = Medium decode timing.
Data Parity Error Detected (DPD) — R/WC.
0 = Conditions described below not met.
1 = The Chipset sets this bit when all of the following three conditions are met:
• The bridge is the initiator on PCI.
• PERR# is detected asserted or a parity error is detected internally
• BCTRL.PERE (D30:F0:3E bit 0) is set.
Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to
PCI target logic is capable of receiving fast back-to-back cycles.
Reserved
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable
only.
Reserved
12.1.13 MEMBASE_LIMIT—Memory Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 20h–23h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
This register defines the base and limit, aligned to a 1-MB boundary, of the non-
prefetchable memory area of the bridge. Accesses that are within the ranges specified
in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside
the ranges specified will be accepted by the bridge if CMD.BME is set.
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Datasheet