82NM10 Datasheet, PDF (334/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.3.17 RMCP_SNUM—RMCP Sequence Number Register
(ASF Controller—B1:D8:F0)
Offset Address: F4h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is a means for software to read the current sequence number that
hardware is using in RMCP packets. Software can also change the value. Software
should only write to this register while the GLOBAL ENABLE is off.
Bit
Description
7:0 RMCP Sequence Number (RSEQ_VAL) — R/W. This is the current sequence number of
the RMCP packet being sent or the sequence number of the next RMCP packet to be
sent. This value can be set by software. At reset, it defaults to 00h. If the sequence
number is not FFh, the ASF controller will automatically increment this number by one
(or rollover to 00h if incrementing from FEh) after a successful RMCP packet
transmission.
11.3.18 SP_MODE—Special Modes Register
(ASF Controller—B1:D8:F0)
Offset Address: F5h
Default Value: x0h
Attribute:
Size:
R/WC, RO
8 bits
The register contains miscellaneous functions.
Bit
Description
7 SMBus Activity Bit (SPE_ACT) — RO.
1 = ASF controller is active with a SMBus transaction. This is an indicator to software
that the ASF controller is still processing commands on the SMBus.
6 Watchdog Status (SPE_WDG) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a watchdog expiration occurs.
5 Link Loss Status (SPE_LNK) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a link loss occurs (link is down for more than 5 seconds).
4:0 Reserved
11.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register
(ASF Controller—B1:D8:F0)
Offset Address: F6h
Default Value: 10h
Attribute:
Size:
R/W
8 bits
This register is used to load and hold the value (in increments of 5 ms) for the polling
timer. This value determines how often the ASF polling timer expires which determines
the minimum idle time between sensor polls.
334
Datasheet