82NM10 Datasheet, PDF (588/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.1.39 VC0CAP—VC0 Resource Capability Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 110h–113h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
23 Reserved.
22:16 Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
15 Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
14 Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
13:8 Reserved.
7:0 Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
18.1.40 VC0CTL—VC0 Resource Control Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 114h–117h
Default Value: 800000FFh
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31 VC0 Enable — RO. Hardwired to 1 for VC0.
30:27 Reserved.
26:24 VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0.
23:20 Reserved.
19:17 Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
16 Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
15:8 Reserved.
7:0 TC/VC0 Map — R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits
[7:1] are implemented as R/W bits.
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Datasheet