82NM10 Datasheet, PDF (422/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.3.6
13.8.3.7
LV2 — Level 2 Register (Netbook Only)
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
Attribute:
Size:
Usage:
RO
8-bit
ACPI or Legacy
Bit
Description
7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a level 2 power state” (C2) to the clock control logic. This will
cause the STPCLK# signal to go active, and stay active until a break event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
NOTE: This register should not be used by Intel^® iA64 processors or systems with more than 1
logical processor, unless appropriate semaphoring software has been put in place to ensure
that all threads/processors are ready for the C2 state when the “read to this register”
instruction occurs.
LV3—Level 3 Register (Netbook Only)
I/O Address:
Default Value:
Lockable:
PMBASE + 15h (ACPI P_BLK + 5)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Bit
Description
7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C3 power state” to the clock control logic. The C3 state
persists until a break event occurs.
NOTES:
1.
If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a
LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and
LVL3 registers (which is not permitted), the Chipset on Netbook platform will ignore the
LVL3 read, and only perform a C2 transition.
2.
This register should not be used by iA64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C3 state when the “read to this register”
instruction occurs.
422
Datasheet