82NM10 Datasheet, PDF (115/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.9.2
5.9.2.1
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by Chipset.
4. Upon observing its own interrupt acknowledge cycle on PCI, Chipset converts it into
the two cycles that the internal 8259 pair can respond to. Each cycle appears as an
interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt
controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA#
pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. If no interrupt request is present because the request was too
short in duration, the PIC returns vector 7 from the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
Initialization Command Words (ICWx)
Before operation can begin, each 8259 must be initialized. In Chipset, this is a four
byte sequence. The four initialization command words are referred to by their
acronyms: ICW1, ICW2, ICW3, and ICW4.
The base address for each 8259 initialization command word is a fixed location in the
I/O memory space: 20h for the master controller, and A0h for the slave controller.
ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, Chipset PIC expects three
more byte writes to 21h for the master controller, or A1h for the slave controller, to
complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
transition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
Datasheet
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