82NM10 Datasheet, PDF (419/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.3.3
PM1_CNT—Power Management 1 Control
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
00000000h
No
Bits 0–7: Core,
Bits 8–12: RTC,
Bits 13–15: Resume
Attribute:
Size:
Usage:
R/W, WO
32-bit
ACPI or Legacy
Bit
Description
31:14
13
12:10
Reserved.
Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into
the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system
should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
Code
000b
001b
010b
011b
100b
101b
110b
111b
Master Interrupt
ON: Typically maps to S0 state.
Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to
assert CPUSLP# to put processor in sleep state: Typically, maps to
S1 state.
Reserved
Reserved
Reserved
Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps
to S4 state.
Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically
maps to S5 state.
9:3 Reserved.
2
Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software
has a corresponding enable and status bits to control its ability to receive ACPI
events.
Datasheet
419