82NM10 Datasheet, PDF (164/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
16. After step 1 (second timeout), if a reset is attempted (using a button that pulses
PWROK low or via the message on the SMBus slave I/F), Chipset attempts to reset
the system.
17. If step 16 (reset attempt) is successful, the BIOS is run. Chipset continues sending
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
18. If step 16 (reset attempt), is unsuccessful, Chipset continues sending heartbeats.
Chipset does not attempt to reboot the system again without external intervention.
(See note 3)
If the system is in a G1 (S1–S4) state, Chipset sends a heartbeat message every 30–
32 seconds. If an event occurs prior to the system being shutdown, Chipset
immediately sends an event message with the next incremented sequence number.
After the event message, Chipset resumes sending heartbeat messages.
Notes for previous two numbered lists.
1. Normally, Chipset does not send heartbeat messages while in the G0 state (except
in the case of a lockup). However, if a hardware event (or heartbeat) occurs just as
the system is transitioning into a G0 state, the hardware continues to send the
message even though the system is in a G0 state (and the status bits may indicate
this).
These messages are sent via the SMBus. Chipset abides by the SMBus rules
associated with collision detection. It delays starting a message until the bus is idle,
and detects collisions. If a collision is detected Chipset waits until the bus is idle,
and tries again.
2. WARNING: It is important the BIOS clears the SECOND_TO_STS bit, as the alerts
interfere with the LAN device driver from working properly. The alerts reset part of
the LAN controller and would prevent an operating system’s device driver from
sending or receiving some messages.
3. A system that has locked up and can not be restarted with power button press is
assumed to have broken hardware (bad power supply, short circuit on some bus,
etc.), and is beyond chipset’s recovery mechanisms.
4. A spurious alert could occur in the following sequence:
— The processor has initiated an alert using the SEND_NOW bit
— During the alert, the THRM#, INTRUDER# or GPIO11 changes state
— The system then goes to a non-S0 state.
Once the system transitions to the non-S0 state, it may send a single alert with an
incremental SEQUENCE number.
5. An inaccurate alert message can be generated in the following scenario
— The system successfully boots after a second watchdog Timeout occurs.
— PWROK goes low (typically due to a reset button press) or a power button
override occurs (before the SECOND_TO_STS bit is cleared).
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Datasheet