82NM10 Datasheet, PDF (644/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
1:0 Power State (PS) — R/W. This field is used both to determine the current power state
of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3_HOT state
NOTE: When in the D3_HOT state, the controller’s configuration space is available, but
the I/O and memory spaces are not. Type 1 configuration cycles are also not
accepted. Interrupts are not required to be blocked as software will disable
interrupts prior to placing the port into D3HOT. If software attempts to write a
‘10’ or ‘01’ to these bits, the write will be ignored.
19.1.44 MPC—Miscellaneous Port Configuration Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: D8h–DBh
Default Value: 00110000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31 Power Management SCI Enable (PMCE) — R/W.
0 = Disable. SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is
detected.
30 Hot Plug SCI Enable (HPCE) — R/W.
0 = Disable. SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
29 Link Hold Off (LHO)— R/W.
0 = Not in Link Hold Off.
1 = The port will not take any TLP. This is used during loopback mode to fill up the
downstream queue.
28 Address Translator Enable (ATE) — R/W. This bit is used to enable address
translation via the AT bits in this register during loopback mode.
0 = Disable.
1 = Enable.
27 Reserved.
26 Invalid Receive Bus Number Check Enable (IRBNCE) — R/W.
0 = Disable.
1 = Enable. Receive transaction layer will signal an error if the bus number of a Memory
request does not fall within the range between SCBN and SBBN. If this check is
enabled and the request is a memory write, it is treated as an Unsupported
Request. If this check is enabled and the request is a non-posted memory read
request, the request is considered a Malformed TLP and a fatal error.
NOTE: Messages, IO, Configuration, and Completions are not checked for valid bus
number.
644
Datasheet