82NM10 Datasheet, PDF (432/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
12
Device Monitor Status (DEVMON_STS) — RO.
0 = SMI# not caused by Device Monitor.
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not
sticky, so writes to this bit will have no effect.
11
Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit
by writing a 1 to it.
0 = Indicates that there has been no access to the power management
microcontroller range (62h or 66h).
1 = Set if there has been an access to the power management microcontroller
range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC
Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11).
Note that this implementation assumes that the Microcontroller is on LPC. If
this bit is set, and the MCSMI_EN bit is also set, the Chipset will generate an
SMI#.
10
GPI_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS
register that are also set up to cause an SMI# (as indicated by the GPI_ROUT
registers) and have the corresponding bit set in the ALT_GP_SMI_EN register.
Bits that are not routed to cause an SMI# will have no effect on this bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
9
GPE0_STS — RO. This bit is a logical OR of the bits 14:10, 8:2, and 0 in the
GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in
the GPE0_EN register (PMBASE + 2Ch).
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
8
PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register
(offset PMBASE+00h) that can cause an SMI#.
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
7
Reserved
6
SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software SMI# Timer has Not expired.
1 = Set by the hardware when the Software SMI# Timer expires.
5
APM_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = No SMI# generated by write access to APM Control register with APMCH_EN
bit set.
1 = SMI# was generated by a write access to the APM Control register with the
APMC_EN bit set.
4
SLP_SMI_STS — R/WC. Software clears this bit by writing a 1 to the bit
location.
0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also
set.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when
SLP_SMI_EN bit is also set.
3
LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits
in the USB Legacy Keyboard/Mouse Control Registers ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
432
Datasheet