82NM10 Datasheet, PDF (460/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
Bit
Description
6 Configure Flag (CF) — R/W. This bit has no effect on the hardware. It is provided only
as a semaphore service for software.
0 = Indicates that software has not completed host controller configuration.
1 = HCD software sets this bit as the last action in its process of configuring the host
controller.
5 Software Debug (SWDBG) — R/W. The SWDBG bit must only be manipulated when
the controller is in the stopped state. This can be determined by checking the HCHalted
bit in the USBSTS register.
0 = Normal Mode.
1 = Debug mode. In SW Debug mode, the host controller clears the Run/Stop bit after
the completion of each USB transaction. The next transaction is executed when
software sets the Run/Stop bit back to 1.
4 Force Global Resume (FGR) — R/W.
0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global
Resume signal. At that time all USB devices should be ready for bus activity. The 1
to 0 transition causes the port to send a low speed EOP signal. This bit will remain
a 1 until the EOP has completed.
1 = Host controller sends the Global Resume signal on the USB, and sets this bit to 1
when a resume event (connect, disconnect, or K-state) is detected while in global
suspend mode.
3 Enter Global Suspend Mode (EGSM) — R/W.
0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes
this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or
after writing bit 4 to 0.
1 = Host controller enters the Global Suspend mode. No USB transactions occur during
this time. The Host controller is able to receive resume signals from USB and
interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared
prior to setting this bit.
2 Global Reset (GRESET) — R/W.
0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified
in Chapter 7 of the USB Specification.
1 = Global Reset. The host controller sends the global reset signal on the USB and then
resets all its logic, including the internal hub registers. The hub registers are reset
to their power on state. Chip Hardware Reset has the same effect as Global Reset
(bit 2), except that the host controller does not send the Global Reset on USB.
1 Host Controller Reset (HCRESET) — R/W. The effects of HCRESET on Hub registers
are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET
affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port.
HCRESET resets the state machines of the host controller including the Connect/
Disconnect state machine (one for each port). When the Connect/Disconnect state
machine is reset, the output that signals connect/disconnect are negated to 0,
effectively signaling a disconnect, even if a device is attached to the port. This virtual
disconnect causes the port to be disabled. This disconnect and disabling of the port
causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the
PORTSC (D29:F0/F1/F2/F3:BASE + 10h) to get set. The disconnect also causes bit 8 of
PORTSC to reset. About 64 bit times after HCRESET goes to 0, the connect and low-
speed detect will take place, and bits 0 and 8 of the PORTSC will change accordingly.
0 = Reset by the host controller when the reset process is complete.
1 = Reset. When this bit is set, the host controller module resets its internal timers,
counters, state machines, etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated.
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