82NM10 Datasheet, PDF (332/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.3.13 PET_SEQ1—PET Sequence 1 Register
(ASF Controller—B1:D8:F0)
Offset Address: F0h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register (low byte) holds the current value of the PET sequence number. This field
is read/write-able through this register, and is also automatically incremented by the
hardware when new PET packets are generated. By policy, software should not write to
this register unless transmission is disabled.
Bit
Description
7:0 PET Sequence Byte 1 (PSEQ1_VAL) — R/W. This field provides the low byte.
11.3.14 PET_SEQ2—PET Sequence 2 Register
(ASF Controller—B1:D8:F0)
Offset Address: F1h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register (high byte) holds the current value of the PET sequence number. This field
is read/write-able through this register, and is also automatically incremented by the
hardware when new PET packets are generated. By policy, software should not write to
this register unless transmission is disabled.
Bit
Description
7:0 PET Sequence Byte 2 (PSEQ2_VAL) — R/W. This field provides the high byte.
11.3.15 STA—Status Register
(ASF Controller—B1:D8:F0)
Offset Address: F2h
Default Value: 40h
Attribute:
Size:
R/W
8 bits
This register gives status indication about several aspects of ASF.
Bit
Description
7 EEPROM Loading (STA_LOAD) — R/W. EEPROM defaults are in the process of being
loaded when this bit is a 1.
6 EEPROM Invalid Checksum Indication (STA_ICRC) — R/W. This bit should be
read only after the EEC_LOAD bit is a 0.
0 = Valid
1 = Invalid checksum detected for ASF portion of the EEPROM.
5:4 Reserved
3 Power Cycle Status (STA_CYCLE) — R/W.
0 = Software clears this bit by writing a 1.
1 = This bit is set when a Power Cycle operation has been issued.
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Datasheet