82NM10 Datasheet, PDF (539/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.2.2.2
Note:
Bit
Description
0 Run/Stop (RS) — R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.
The Host controller continues execution as long as this bit is set. When this bit is
set to 0, the Host controller completes the current transaction on the USB and then
halts. The HCHalted bit in the USB2.0_STS register indicates when the Host
controller has finished the transaction and has entered the stopped state.
Software should not write a 1 to this field unless the host controller is in the Halted
state
(i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately
when the Run bit is set.
The following table explains how the different combinations of Run and Halted should
be interpreted:
Run/Stop
0b
0b
1b
1b
Halted
0b
1b
0b
1b
Interpretation
In the process of halting
Halted
Running
Invalid - the HCHalted bit clears immediately
Memory read cycles initiated by the EHC that receive any status other than Successful
will result in this bit being cleared.
NOTE: The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
USB2.0_STS—USB 2.0 Status Register
Offset:
MEM_BASE + 24h–27h
Default Value: 00001000h
Attribute:
Size:
R/WC, RO
32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in section 4 of the EHCI specification for additional
information concerning USB 2.0 interrupt conditions.
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
Bit
Description
31:16 Reserved. These bits are reserved and should be set to 0 when writing this register.
15 Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the
Asynchronous Schedule.
0 = Status of the Asynchronous Schedule is disabled. (Default)
1 = Status of the Asynchronous Schedule is enabled.
NOTE: The Host controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous Schedule
Enable bit (D29:F7:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD register. When
this bit and the Asynchronous Schedule Enable bit are the same value, the
Asynchronous Schedule is either enabled (1) or disabled (0).
Datasheet
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