82NM10 Datasheet, PDF (430/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
3
LEGACY_USB_EN — R/W.
0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
2
BIOS_EN — R/W.
0 = Disable.
1 = Enables the generation of SMI# when ACPI software writes a 1 to the
GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit
(D31:F0:PMBase + 34h:bit 2), which gets set when software writes 1 to
GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI#
will be generated when BIOS_EN gets set.
1
End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI
signal to the processor. This bit must be set for the Chipset to assert SMI# low to
the processor after SMI# has been asserted previously.
0 = Once the Chipset asserts SMI# low, the EOS bit is automatically cleared.
1 = When this bit is set to 1, SMI# signal will be deasserted for 4 PCI clocks
before its assertion. In the SMI handler, the processor should clear all
pending SMIs (by servicing them and then clearing their respective status
bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-
assert SMI upon detection of an SMI event and the setting of a SMI status bit.
NOTE: Chipset is able to generate 1st SMI after reset even though EOS bit is not
set. Subsequent SMI require EOS bit is set.
0
GBL_SMI_EN — R/W.
0 = No SMI# will be generated by Chipset. This bit is reset by a PCI reset event.
1 = Enables the generation of SMI# in the system upon any enabled SMI event.
NOTE: When the SMI_LOCK bit is set, this bit cannot be changed.
13.8.3.13 SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 34h
00000000h
No
Core
Attribute:
Size:
Usage:
RO, R/WC
32-bit
ACPI or Legacy
Note:
If the corresponding _EN bit is set when the _STS bit is set, the Chipset will cause an
SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs
of other registers that have enable bits). The Chipset uses the same GPE0_EN register
(I/O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose
input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec.
Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS,
and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns
off the enabled bit for any GPIx input signals that are not indicated as SCI general-
purpose events at boot, and exit from sleeping states. BIOS should define a dummy
control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.
Bit
31:27
Reserved
Description
430
Datasheet