82NM10 Datasheet, PDF (70/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Pin States
3.3
Power Planes for Input Signals
Table 3-27 shows the power plane associated with each input signal, as well as what
device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
The chipset suspend well signal states are indeterminate and undefined and may glitch
prior to RSMRST#deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4#
and SLP_S5#. These signals are determinate and defined prior to RSMRST#
deassertion.
The chipset core well signal states are indeterminate and undefined and may glitch
prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These
signals are determinate and defined prior to PWROK assertion.
Table 3-27.Power Plane for Input Signals (Sheet 1 of 2)
Signal Name
Power
Well
Driver During Reset C3/C4
S1
S3_COLD
2
A20GATE
HDA_SDIN[2:0
] (Intel HD
Audio Mode)
BM_BUSY# /
GPIO0²
BATLOW#
CLK14
CLK48
DMI_CLKP
DMI_CLKN
EE_DIN
FERR#
PERp[4:1],
PERn[4:1]
DMI[3:0]RXP,
DMI[3:0]RXN
INTRUDER#
INTVRMEN
Core
Suspend
Core
Suspend
Core
Core
Core
LAN
Core
Core
Core
RTC
RTC
External
Microcontroller
Static Static
Low
Intel HD Audio Codec Driven
Low
Low
Graphics Component
[(G)MCH]
Power Supply
Clock Generator
Clock Generator
Clock Generator
Driven
High
High
High
Running Running
Running Running
Running Running
Low
High
Low
Low
Low
EEPROM Component
Processor
PCI Express* Device
Driven
Static
Driven
Driven
Static
Driven
Note 1
Low
Driven
(G)MCH
Driven Driven
Low
External Switch
External Pull-up or
Pull-down
Driven
Driven
Driven
Driven
Driven
Driven
S4/S5
Low
Low
Low
High
Low
Low
Low
Note 1
Low
Driven
Low
Driven
Driven
70
Datasheet