82NM10 Datasheet, PDF (435/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
7 PIRQBF_ACT_STS — R/WC. PIRQ[B or F].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
6 PIRQAE_ACT_STS — R/WC. PIRQ[A or E].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
5:1 Reserved
0 IDE_ACT_STS — R/WC. IDE Primary Drive 0 and Drive 1.
0 = Indicates that there has been no access to this device’s I/O range.
1 = This device’s I/O range has been accessed. The enable bit is in the ATC register
(D31:F1:Offset C0h). Clear this bit by writing a 1 to the bit location.
13.8.3.18 SS_CNT— Intel SpeedStep^® Technology
Control Register (Netbook Only)
I/O Address:
Default Value
Lockable:
Power Well:
PMBASE +50h
01h
No
Core
Attribute:
Size:
Usage:
R/W (special)
8-bit
ACPI/Legacy
Note:
Writes to this register will initiate an Intel SpeedStep technology transition that
involves a temporary transition to a C3-like state in which the STPCLK# signal will go
active. An Intel SpeedStep technology transition always occur on writes to the
SS_CNT register, even if the value written to SS_STATE is the same as the previous
value (after this “transition” the system would still be in the same Intel SpeedStep
technology state). If the SS_EN bit is 0, then writes to this register will have no effect
and reads will return 0.
Bit
Description
7:1 Reserved
0 SS_STATE (Intel SpeedStep^® technology State) — R/W (Special). When this bit is
read, it returns the last value written to this register. By convention, this will be the
current Intel SpeedStep technology state. Writes to this register causes a change to the
Intel SpeedStep technology state indicated by the value written to this bit. If the new
value for SS_STATE is the same as the previous value, then transition will still occur.
0 = High power state.
1 = Low power state
NOTE: This is only a convention because the transition is the same regardless of the
value written to this bit.
Datasheet
435