82NM10 Datasheet, PDF (306/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.1.13 SVID — Subsystem Vendor Identification
(LAN Controller—B1:D8:F0)
Offset Address: 2Ch–2D
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:0 Subsystem Vendor ID (SVID) — RO. See Section 11.1.14 for details.
11.1.14 SID — Subsystem Identification
(LAN Controller—B1:D8:F0)
Offset Address: 2Eh–2Fh
Default Value: 0000h
Bit
15:0 Subsystem ID (SID) — RO.
Attribute:
Size:
Description
RO
16 bits
Note:
The chipset’s integrated LAN controller provides support for configurable Subsystem ID
and Subsystem Vendor ID fields. After reset, the LAN controller automatically reads
addresses Ah through Ch, and 23h of the EEPROM. The LAN controller checks bits
15:13 in the EEPROM word Ah, and functions according to Table 11-112.
Table 11-112.Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM
Bits 15:14
Bit
13
Device
ID¹
Vendor ID
Revision ID²
Subsystem ID
Subsystem
Vendor ID
11b, 10b,
00b
01b
01b
X
1051h
8086h
0b Word 23h 8086h
1b Word 23h Word Ch
00h
00h
80h + Word
Ah,
bits 10:8
0000h
Word Bh
Word Bh
0000h
Word Ch
Word Ch
NOTES:
1.
The Device ID is loaded from Word 23h only if the value of Word 23h is not 0000h or FFFFh
2.
The Revision ID is subject to change according to the silicon stepping.
11.1.15CAP_PTR — Capabilities Pointer
(LAN Controller—B1:D8:F0)
Offset Address:34hAttribute:
Default Value: DCh
RO
Size:
8 bits
Bit
Description
7:0 Capabilities Pointer (CAP_PTR) — RO. Hardwired to DCh to indicate the offset
within configuration space for the location of the Power Management registers.
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