82NM10 Datasheet, PDF (564/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.2.3
17.2.4
17.2.5
17.2.6
HST_CMD—Host Command Register (SMBUS—D31:F3)
Register Offset: SMBASE + 03h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 This 8-bit field is transmitted by the host controller in the command field of the SMBus
protocol during the execution of any command.
XMIT_SLVA—Transmit Slave Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 04h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
Bit
Description
7:1 Address — R/W. This field provides a 7-bit address of the targeted slave.
0 RW — R/W. Direction of the host transfer.
0 = Write
1 = Read
HST_D0—Host Data 0 Register (SMBUS—D31:F3)
Register Offset: SMBASE + 05h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Data0/Count — R/W. This field contains the 8-bit data sent in the DATA0 field of the
SMBus protocol. For block write commands, this register reflects the number of bytes to
transfer. This register should be programmed to a value between 1 and 32 for block
counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host
controller does not check or log invalid block counts.
HST_D1—Host Data 1 Register (SMBUS—D31:F3)
Register Offset: SMBASE + 06h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus
protocol during the execution of any command.
564
Datasheet