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| 82NM10 Datasheet, PDF (262/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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Register and Memory Mapping
Table 9-109.Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
Memory Range
0000 0000hâ000D FFFFh
0010 0000hâTOM
(Top of Memory)
Target
Main Memory
000E 0000hâ000E FFFFh Firmware Hub
000F 0000hâ000F FFFFh Firmware Hub
FEC0 0000hâFEC0 0100h
FED4 0000hâFED4 0FFFh
FFC0 0000hâFFC7 FFFFh
FF80 0000hâFF87 FFFFh
FFC8 0000hâFFCF FFFFh
FF88 0000hâFF8F FFFFh
FFD0 0000hâFFD7 FFFFh
FF90 0000hâFF97 FFFFh
FFD8 0000hâFFDF FFFFh
FF98 0000hâFF9F FFFFh
FFE0 000hâFFE7 FFFFh
FFA0 0000hâFFA7 FFFFh
FFE8 0000hâFFEF FFFFh
FFA8 0000hâFFAF FFFFh
FFF0 0000hâFFF7 FFFFh
FFB0 0000hâFFB7 FFFFh
I/O APIC inside Chipset
TPM on LPC
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
FFF8 0000hâFFFF FFFFh Firmware Hub (or PCI)1
FFB8 0000hâFFBF FFFFh
FF70 0000hâFF7F FFFFh
FF30 0000hâFF3F FFFFh
FF60 0000hâFF6F FFFFh
FF20 0000hâFF2F FFFFh
FF50 0000hâFF5F FFFFh
FF10 0000hâFF1F FFFFh
FF40 0000hâFF4F FFFFh
FF00 0000hâFF0F FFFFh
4 KB anywhere in 4-GB
range
1 KB anywhere in 4-GB
range
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Firmware Hub (or PCI)1
Integrated LAN
Controller2
USB EHCI Controller 2
Dependency/Comments
TOM registers in Host controller
Bit 6 in Firmware Hub Decode Enable
register is set
Bit 7 in Firmware Hub Decode Enable
register is set
Bit 8 in Firmware Hub Decode Enable
register is set
Bit 9 in Firmware Hub Decode Enable
register is set
Bit 10 in Firmware Hub Decode Enable
register is set
Bit 11 in Firmware Hub Decode Enable
register is set
Bit 12 in Firmware Hub Decode Enable
register is set
Bit 13 in Firmware Hub Decode Enable
register is set
Bit 14 in Firmware Hub Decode Enable
register is set
Always enabled.
The top two, 64 KB blocks of this range
can be swapped, as described in
Section 7.4.1.
Bit 3 in Firmware Hub Decode Enable
register is set
Bit 2 in Firmware Hub Decode Enable
register is set
Bit 1 in Firmware Hub Decode Enable
register is set
Bit 0 in Firmware Hub Decode Enable
register is set
Enable via BAR in Device 29:Function 0
(Integrated LAN Controller)
Enable via standard PCI mechanism
(Device 29, Function 7)
262
Datasheet
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