82NM10 Datasheet, PDF (643/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.42 PMC—PCI Power Management Capabilities Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: A2h–A3h
Default Value: C802h
Attribute:
Size:
RO
16 bits
Bit
Description
15:11
PME_Support (PMES) — RO. This field indicates PME# is supported for states D0,
D3_HOT and D3_COLD. The root port does not generate PME#, but reporting that it does is
necessary for some legacy operating systems to enable PME# in devices connected
behind this root port.
10 D2_Support (D2S) — RO. The D2 state is not supported.
9 D1_Support (D1S) — RO The D1 state is not supported.
8:6 Aux_Current (AC) — RO. This field reports 375 mA maximum suspend well current
required when in the D3_COLD state.
5 Device Specific Initialization (DSI) — RO. This bit indicates that no device-specific
initialization is required.
4 Reserved
3 PME Clock (PMEC) — RO. This bit indicates that PCI clock is not required to generate
PME#.
2:0 Version (VS) — RO. This field indicates support for Revision 1.1 of the PCI Power
Management Specification.
19.1.43 PMCS—PCI Power Management Control and Status
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: A4h–A7h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:24 Reserved
23 Bus Power / Clock Control Enable (BPCE). Reserved per PCI Express* Base
Specification, Revision 1.0a.
22 B2/B3 Support (B23S). Reserved per PCI Express* Base Specification, Revision
1.0a.
21:16 Reserved
15 PME Status (PMES) — RO. This bit indicates a PME was received on the downstream
link.
14:9 Reserved
8 PME Enable (PMEE) — R/W. Indicates PME is enabled. The root port takes no action
on this bit, but it must be R/W for some legacy operating systems to enable PME# on
devices connected to this root port.
0 = Disable.
1 = Enable.
NOTE: This bit is sticky and resides in the resume well. The reset for this bit is
RSMRST# which is not asserted during a warm reset.
7:2 Reserved
Datasheet
643