82NM10 Datasheet, PDF (90/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.3.2 Serial EEPROM Interface
The serial EEPROM stores configuration data for Chipset integrated LAN controller and
is a serial in/serial out device. The LAN controller supports a 64-register or 256-register
size EEPROM and automatically detects the EEPROM’s size. The EEPROM should operate
at a frequency of at least 1 MHz.
All accesses, either read or write, are preceded by a command instruction to the
device. The address field is six bits for a 64-register EEPROM or eight bits for a 256-
register EEPROM. The end of the address field is indicated by a dummy 0 bit from the
EEPROM that indicates the entire address field has been transferred to the device. An
EEPROM read instruction waveform is shown in Figure 5-7.
Figure 5-7. 64-Word EEPROM Read Instruction Waveform
EE_SHCLKK
EE_CS
EE_DIN
EE_DOUT
A₅
A₄
A₃
A₂
AA₁₀ A₀
READ OP code
D₁₅
D₀
5.3.3
5.3.3.1
The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch,
and Dh) of the EEPROM after the deassertion of Reset.
CSMA/CD Unit
Chipset integrated LAN controller CSMA/CD unit implements both the IEEE 802.3
Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all
the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, etc.).
The LAN controller CSMA/CD unit interfaces to the 82562ET/EM/EZ/EX 10/100 Mbps
Ethernet through chipset’s LAN Connect interface signals.
Full Duplex
When operating in full-duplex mode, the LAN controller can transmit and receive
frames simultaneously. Transmission starts regardless of the state of the internal
receive path. Reception starts when the platform LAN Connect component detects a
valid frame on its receive differential pair. Chipset integrated LAN controller also
supports the IEEE 802.3x flow control standard, when in full-duplex mode.
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Datasheet